Modern automotive electronic control units (ECUs) are integrating more and more functionality. This trend is driven by technology scaling that enables a high level of integration, and by cost considerations of a highly competitive automotive industry that forces a reduction in the total number of ECUs per car. Electronics play an increasingly important role in providing advanced driving assistance functions, and in particular, preventing hazards that may reduce the number of fatal injuries.
In the context of safety applications, microcontrollers of ECUs which serve vital functions have been developed with redundant hardware structures. Although current sub-micron technologies (65 nm and below) may enable the area overhead required to implement redundant hardware structures, power consumption is the main limiting factor to realizing such redundant structures in practice. Hardware structure redundancy is not only the current state of the art for CPUs, but is sometimes extended to functions performed by interrupt controllers and direct memory access (DMA) engines. DMA engines play a key role in many safety applications, especially in the acquisition of safety-related information.
It would be desirable to provide an optimal use of DMA hardware resources by taking advantage of existing hardware redundancies to provide an on-demand high integrity operation mode where several DMA resources may not only be used concurrently, but whose data resources may be checked at the DMA level.